UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 742

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remarks 1. n: DMA channel number (n = 0, 1)
Caution In example 3, the system is not required to wait two clock cycles after the DWAITn bit is set to 1. In
• Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used
addition, the system does not have to wait two clock cycles after clearing the DSTn bit to 0,
because more than two clock cycles elapse from when the DSTn bit is cleared to 0 to when the
DENn bit is cleared to 0.
2. 1 clock: 1/f
DWAIT0 = 1
DWAIT1 = 1
DWAIT0 = 0
DWAIT1 = 0
CLK
DENn = 0
DSTn = 0
Figure 18-13. Forced Termination of DMA Transfer (2/2)
(f
CLK
: CPU clock)
Example 3
• Procedure for forcibly terminating the DMA
transfer for both channels if both channels are used
DWAIT0 = 1
DWAIT1 = 1
DWAIT0 = 0
DWAIT1 = 0
DEN0 = 0
DEN1 = 0
DST0 = 0
DST1 = 0
CHAPTER 18 DMA CONTROLLER
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