UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 249

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(4) CPU operating with 20 MHz internal high-speed oscillation clock (J) after reset release (A)
(5) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(A) → (B) → (J)
Status Transition
Status Transition
(B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
(B) → (C)
(external main clock)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
Note
Notes 1. The CMC register can be changed only once after reset release. This setting is not necessary if it has
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
Remarks 1. ×: don’t care
(Setting sequence of SFR registers)
2. Set the oscillation stabilization time as follows.
3. FSEL = 1 when f
Check that V
Setting Flag of SFR Register
(Setting sequence of SFR registers)
already been set.
If a divided clock is selected and f
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2. (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
Setting Flag of SFR Register
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/6)
DD
≥ 2.7 V and set DSCON = 1.
CLK
> 10 MHz
EXCLK
Unnecessary if these registers
0
0
1
CMC Register
are already set
CLK
DSCCTL Register
OSCSEL
≤ 10 MHz, use with FSEL = 0 is possible even if f
1
1
1
DSCON
1
Note 1
AMPH
×
0
1
Note
Register
Note 2
Note 2
Note 2
OSTS
Unnecessary if the CPU is operating with
Waiting for Oscillation
the high-speed system clock
Stabilization
Necessary
(100
MSTOP
Register
CHAPTER 5 CLOCK GENERATOR
CSC
0
0
0
μ
s)
Register
OSMC
FSEL
1
0/1
Note 3
0
DSCCTL Register
checked
checked
checked
Register
Must be
Must be
OSTC
not be
Must
X
SELDSC
> 10 MHz.
1
MCM0
CKC
Regi
ster
1
1
1
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