UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 454

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
SMRmn
(3) Serial mode register mn (SMRmn)
Symbol
SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock (MCK),
specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or
I
mode.
Rewriting SMRmn is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit can
be rewritten during operation.
SMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0020H.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark
2
C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Operation clock MCK is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (TCLK) is generated.
Transfer clock TCLK is used for the shift register, communication controller, output controller, interrupt controller,
and error controller. When CCSmn = 0, the division ratio of MCK is set by the higher 7 bits of the SDRmn register.
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
CKS
CCS
CKS
STS
mn
mn
mn
mn
15
0
1
0
1
0
1
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Prescaler output clock CKm0 set by SPSm register
Prescaler output clock CKm1 set by SPSm register
Divided operation clock MCK specified by CKSmn bit
Clock input from SCK pin (slave transfer in CSI mode)
Only software trigger is valid (selected for CSI, UART transmission, and simplified I
Valid edge of R
CCS
mn
14
Figure 14-6. Format of Serial Mode Register mn (SMRmn) (1/2)
13
0
X
12
D pin (selected for UART reception)
0
11
0
Selection of operation clock (MCK) of channel n
10
Selection of transfer clock (TCLK) of channel n
0
Selection of start trigger source
9
0
STS
mn
8
After reset: 0020H
7
0
mn0
SIS
6
CHAPTER 14 SERIAL ARRAY UNIT
5
1
R/W
4
0
2
3
0
C).
mn2
MD
2
mn1
MD
1
mn0
MD
0
454