UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 710

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
<R>
78K0R/Lx3
16.8.3 Capacitor split method
The internal voltage reduction circuit and external capacitors (0.47
Only 1/3 bias mode can be set for the capacitor split method.
so current consumption can be reduced.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Note V
Remark Use a capacitor with as little leakage as possible.
The 78K0R/Lx3 microcontrollers contain an internal voltage reduction circuit for generating LCD drive power supplies.
Different from the external resistance division method, there is always no current flowing with the capacitor split method,
LCD Drive Voltage Pin
V
V
V
V
LC0
LC1
LC2
LC3
Drive voltage
Internal reference
voltage generator
generator
LC3
Figure 16-32. Examples of LCD Drive Power Connections (Internal Voltage Boosting Method)
In addition, make C1 a nonpolar capacitor.
can be used as port (P02).
(a) 1/3 bias method
3xV
2xV
LC2
LC2
Bias Method
Table 16-11. LCD Drive Voltages (Capacitor Split Method)
V
V
V
V
V
CAPH
CAPL
DD
LC0
LC1
LC2
LC3
/P02
Note
V
2/3 x V
1/3 x V
DD
C2
C1
DD
DD
C3
C4
Remark Use a capacitor with as little leakage as possible.
Drive voltage
Internal reference
voltage generator
generator
μ
F±30%) are used to generate an LCD drive voltage.
CHAPTER 16 LCD CONTROLLER/DRIVER
In addition, make C1 a nonpolar capacitor.
1/3 Bias Method
(b) 1/4 bias method
4xV
3xV
2xV
LC3
LC3
LC3
V
V
V
V
V
CAPH
CAPL
DD
LC0
LC1
LC2
LC3
C1
C2
C3
C4
C5
710

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