UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 998

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Electrical
specifications
Function
DC
characteristics
Minimum
instruction
execution time
during main
system clock
operation
During
communication
at same potential
(UART mode)
(dedicated baud
rate generator
output)
During
communication
at same potential
(CSI mode)
(master mode,
SCKp... internal
clock output)
During
communication
at same potential
(CSI mode)
(slave mode,
SCKp... external
clock input)
During
communication
at same potential
(simplified I
mode)
During
communication
at different
potential (2.5 V,
3 V) (UART
mode)
(dedicated baud
rate generator
output)
Details of
Function
2
C
P10 to P15, P75, P77, P80 and P82 do not output high level in N-ch open-drain
mode.
The maximum value of V
in the N-ch open-drain mode.
When V
operation or f
divided. The STOP mode may be released during f
Select the normal input buffer for RxDq and the normal output mode for TxDq by
using the PIMg and POMx registers.
Select the normal input buffer for SIp and the normal output mode for SOp and
SCKp by using the PIMg and POMx registers.
Select the normal input buffer for SIp and SCKp and the normal output mode for
SOp by using the PIMg and POMx registers.
Select the normal input buffer and the N-ch open drain output (V
for SDAr and the normal output mode for SCLr by using the PIMg and POMx
registers.
Select the TTL input buffer for RxDq and the N-ch open drain output (V
mode for TxDq by using the PIMg and POMx registers.
DD
< 2.25 V and FSEL = 1, It is prohibited to release STOP mode during f
IH
operation (This must not be performed even if the frequency is
IH
of pins P10 to P15, P75, P77, P80 and P82 is V
Cautions
APPENDIX C LIST OF CAUTIONS
X
operation.).
DD
tolerance) mode
DD
tolerance)
DD
, even
EX
894
913, 915
pp.890,
p.892
p.902
p.906
p.907
p.908
p.910
pp.912,
Page
(38/39)
998