UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 399

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
FR2
A/D Converter Mode Register (ADM)
Notes 1.
Caution When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0
Remark f
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FR1
2.
3.
4.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Other than above
= 0), enable the input gate voltage boost circuit for the A/D converter by using the analog reference
voltage control register (ADVRC), and then set ADCE and ADCS to 1. After the voltage boost circuit
stabilization time (10
been enabled, set ADCS to 1.
CLK
Normal mode 1: 2.7 V ≤ AV
converter is stopped.
Normal mode 2: 2.3 V ≤ AV
converter is operating.
Low voltage mode: 1.8 V ≤ AV
converter is operating.
When T
: CPU/peripheral hardware clock frequency
FR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
= 0 to 50°C and 2.3 V ≤ AV
LV1
0
0
1
LV0
0
1
0
μ
Table 10-2. A/D Conversion Time Selection
s) passes after the input gate voltage boost circuit for the A/D converter has
Setting prohibited
mode 1
mode 2
Normal
Normal
voltage
Mode
mode
Low
Note 1
Note 2
Note 3
DD0
DD0
DD0
≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
240/f
160/f
120/f
100/f
80/f
60/f
40/f
20/f
240/f
160/f
120/f
100/f
80/f
60/f
40/f
20/f
300/f
200/f
150/f
125/f
100/f
75/f
50/f
25/f
DD0
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
≤ 3.6 V.
f
1 MHz
Setting
prohibited
40
20
Setting
prohibited
40
20
Setting
prohibited
50
25
CLK
μ
μ
μ
μ
μ
μ
=
s
s
s
s
s
s
Conversion Time Selection
f
8 MHz
30
20
15
12.5
10
7.5
5
Setting
prohibited
30
20
15
12.5
10
7.5
5
Setting
prohibited
37.5
25
18.8
15.6
12.5
9.38
6.25
Setting
prohibited
CLK
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
s
s
=
μ
μ
s
s
s
s
s
s
s
s
s
μ
μ
μ
μ
μ
μ
s
μ
s
μ
s
s
s
s
s
s
s
s
Note 4
Note 4
Note 4
Note 4
Note 4
CHAPTER 10 A/D CONVERTER
f
10 MHz
24
16
12
10
8
6
Setting
prohibited
24
16
12
10
8
6
Setting
prohibited
30
20
15
12.5
10
7.5
Setting
prohibited
CLK
μ
μ
μ
μ
μ
μ
μ
μ
s
s
μ
μ
μ
μ
s
s
μ
μ
μ
μ
=
μ
s
s
s
s
s
s
s
s
s
s
s
s
μ
s
Note 4
Note 4
s
Note 4
Note 4
Note 4
f
20 MHz
12
8
6
5
Setting
prohibited
12
8
6
5
Setting
prohibited
15
10
7.5
6.25
Setting
prohibited
CLK
μ
μ
μ
μ
μ
μ
μ
s
s
s
μ
s
s
s
μ
μ
=
μ
s
s
s
s
μ
s
s
Note 4
Note 4
Note 4
Note 4
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Conversion
Clock
/12
/8
/6
/5
/4
/3
/2
/12
/8
/6
/5
/4
/3
/2
/12
/8
/6
/5
/4
/3
/2
(f
AD
)
399