UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 102

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address
FFF28H
FFF29H
FFF2AH
FFF2BH
FFF2CH Port mode register 12
FFF2EH
FFF2FH
FFF30H
FFF31H
FFF32H
FFF33H
FFF36H
FFF37H
FFF38H
FFF39H
FFF3AH
FFF3BH
FFF3CH Input switch control register
FFF3EH
FFF3FH
FFF40H
FFF41H
FFF42H
FFF43H
FFF44H
FFF45H
FFF46H
FFF47H
FFF48H
FFF49H
FFF4AH
FFF4BH
FFF50H
FFF51H
FFF52H
FFF58H D/A
FFF59H conversion value setting register W0
FFF5AH D/A
FFF5BH conversion value setting register W1
Port mode register 8
Port mode register 9
Port mode register 10
Port mode register 11
Port mode register 14
Port mode register 15
A/D converter mode register
Analog input channel specification register
A/D converter mode register 1
Operational amplifier control register
Analog reference voltage control register
Key return mode register
External interrupt rising edge enable register 0
External interrupt falling edge enable register 0
External interrupt rising edge enable register 1
External interrupt falling edge enable register 1
Timer input select register 0
Timer input select register 1
LCD mode register
LCD display mode register
LCD clock control register 0
LCD boost level control register
Serial data register 02
Serial data register 03
Serial data register 10
Serial data register 11
IICA shift register
IICA status register
IICA flag register
Special Function Register (SFR) Name
D/A conversion value setting register 0 DACS0
D/A conversion value setting register 1 DACS1
Table 3-5. SFR List (2/5)
PM8
PM9
PM10
PM11
PM12
PM14
PM15
ADM
ADS
ADM1
OAC
ADVRC
KRM
EGP0
EGN0
EGP1
EGN1
ISC
TIS0
TIS1
LCDMD
LCDM
LCDC0
VLCD
TXD1/
SIO10
RXD1
TXD2/
SIO20
RXD2
IICA
IICS
IICF
−
−
−
−
−
−
Symbol
SDR02
SDR03
SDR10
SDR11
DACS
W0
DACS
W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
CHAPTER 3 CPU ARCHITECTURE
1-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
√
√
−
−
−
−
Manipulable Bit
Range
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
√
√
−
√
−
16-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
−
−
−
−
√
−
√
0000H
0000H
0000H
0000H
0000H
0000H
Reset
After
FEH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0FH
00H
00H
00H
00H
00H
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
102