HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 129

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.5
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Bit n
IRQnF
0
1
110
Bit
Initial value
R/W
Note: * Only 0 can be written, to clear the flag.
IRQ Status Register (ISR)
Description
[Clearing conditions]
[Setting conditions]
:
:
:
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
When IRQn interrupt exception handling is executed when falling, rising, or both-edge
detection is set (IRQnSCB = 1 or IRQnSCA = 1)
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
R/(W)*
IRQ7F
7
0
R/(W)*
IRQ6F
6
0
R/(W)*
IRQ5F
5
0
R/(W)*
IRQ4F
4
0
R/(W)*
IRQ3F
3
0
R/(W)*
IRQ2F
2
0
R/(W)*
IRQ1F
1
0
(Initial value)
R/(W)*
(n = 7 to 0)
IRQ0F
0
0