HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 152

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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6.1.3
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Name
Address strobe
Read
High write
Low write
Chip select 0 to 3
Wait
Bus request
Bus request
acknowledge
Table 6.2 summarizes the registers of the bus controller.
Table 6.2
Name
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus control register H
Bus control register L
Notes: 1. Lower 16 bits of the address.
6.1.4
2. Determined by the MCU operating mode.
Pin Configuration
Register Configuration
Bus Controller Pins
Bus Controller Registers
Symbol
AS
RD
HWR
LWR
CS0 to
CS3
WAIT
BREQ
BACK
Abbreviation
ABWCR
ASTCR
WCRH
WCRL
BCRH
BCRL
I/O
Output
Output
Output
Output
Output
Input
Input
Output
Function
Strobe signal indicating that address output on address
bus is enabled.
Strobe signal indicating that external space is being
read.
Strobe signal indicating that external space is to be
written, and upper half (D
Strobe signal indicating that external space is to be
written, and lower half (D
Strobe signal indicating that areas 0 to 3 are selected.
Wait request signal when accessing external 3-state
access space.
Request signal that releases bus to external device.
Acknowledge signal indicating that bus has been
released.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-On
Reset
H'FF/H'00*
H'FF
H'FF
H'FF
H'D0
H'3C
Initial Value
2
7
15
to D
to D
Manual
Reset
Retained
Retained
Retained
Retained
Retained
Retained
0
) of data bus is enabled.
8
) of data bus is enabled.
Address*
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
1
133

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