HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 273

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.9.2
Table 8.15 shows the port D register configuration.
Table 8.15 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read..
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
256
Bit
Initial value
R/W
Modes 1, 2, 4, 5, and 6*
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
Modes 3 and 7*
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
Register Configuration
:
:
:
PD7DDR
W
7
0
PD6DDR
W
6
0
PD5DDR
Abbreviation
PDDDR
PDDR
PORTD
PDPCR
W
5
0
PD4DDR
W
4
0
PD3DDR
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
PD2DDR
W
2
0
PD1DDR
W
1
0
Address *
H'FEBC
H'FF6C
H'FF5C
H'FF73
PD0DDR
W
0
0