HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 626

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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18.4
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (ø).
18.5
The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.
18.6
The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed
clocks (ø/2, ø/4, or ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit
615

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