HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 853

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

TIOR0L—Timer I/O Control Register 0L
844
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Bit
Initial value
Read/Write
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as
TGR0D I/O Control
:
:
:
:
0
1
IOD3
R/W
7
0
0
1
0
1
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer
the TCNT1 count clock, this setting is invalid and input capture is not
generated.
register, this setting is invalid and input capture/output compare is not
generated.
0
1
0
1
0
1
*
IOD2
R/W
0
1
0
1
0
1
0
1
0
1
*
*
6
0
TGR0D
is output
compare
register
TGR0D
is input
capture
register
*2
IOD1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer
IOD0
TGR0C I/O Control
R/W
0
1
4
0
0
1
0
1
register, this setting is invalid and input capture/output compare is not
generated.
IOC3
R/W
0
1
0
1
0
1
*
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
0
1
0
1
0
1
0
1
0
1
*
*
TGR0C
is output
compare
register
TGR0C
is input
capture
register
*1
IOC2
R/W
2
0
*1
H'FFD3
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
IOC1
R/W
1
0
* : Don’t care
IOC0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
* : Don’t care
TPU0