HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 477

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
[3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
[4] After completion of serial transmission, the SCK pin is fixed.
Serial clock
Serial data
TDRE
TEND
TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is
generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the
TxD pin maintains its state.
If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
Figure 12.17 shows an example of SCI operation in transmission.
Serial data reception (clocked synchronous mode)
TXI interrupt
request generated
Figure 12.17 Example of SCI Operation in Transmission
interrupt service routine
Data written to TDR
cleared to 0 in TXI
Bit 7
and TDRE flag
Transfer direction
Bit 0
1 frame
TXI interrupt
request generated
Bit 7
Bit 0
Bit 1
Bit 6
TEI interrupt
request generated
Bit 7
463