HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 95

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.3
3.3.1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and
8-bit bus mode is set, immediately after a reset.
Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries
bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus
mode switches to 16 bits and port E becomes a data bus.
3.3.2
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and
8-bit bus mode is set. immediately after a reset.
Ports B and C function as input ports immediately after a reset. They can each be set to output
addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D
functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit
access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a
data bus.
The amount of on-chip ROM that can be used is limited to 56 kbytes.
3.3.3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but
external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
The amount of on-chip ROM that can be used is limited to 56 kbytes.
3.3.4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P1
and part of port F carries bus control signals. Pins P1
reset. Each of these pins can be set to output addresses by setting the corresponding bit in the data
direction register (DDR) to 1.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if
8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3
to P1
Operating Mode Descriptions
Mode 1 (ZTAT, Mask ROM, and ROMless Versions Only)
Mode 2 *
Mode 3 *
Mode 4 *
0
, ports A, B and C function as an address bus, ports D and E function as a data bus,
1
1
2
(ZTAT and Mask ROM Versions Only)
(ZTAT and Mask ROM Versions Only)
3
to P1
0
function as inputs immediately after a
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