HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 520

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

14.2
14.2.1
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
14.3.
ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower
byte, data transfer is performed via a temporary register (TEMP). For details, see section 14.3,
Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop
mode.
Table 14.3 Analog Input Channels and Corresponding ADDR Registers
Group 0
AN0
AN1
AN2
AN3
Bit
Initial value
R/W
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Analog Input Channel
:
:
:
AD9
15
R
0
AD8
14
R
Group 1
AN4
AN5
AN6
AN7
0
AD7
13
R
0
AD6
12
R
0
AD5
11
R
0
AD4
10
R
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD3
R
9
0
AD2
R
8
0
AD1
R
7
0
AD0
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
—
R
2
0
—
R
1
0
—
507
R
0
0