HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 595

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

FLER bit setting conditions are as follows:
Error protection is released only by a reset and in hardware standby mode.
Figure 17.23 shows the flash memory state transition diagram.
Legend:
RD: Memory read possible
VF:
PR: Programming possible
ER: Erasing possible
When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
Immediately after exception handling (excluding a reset) during programming/erasing
When a SLEEP instruction (including software standby) is executed during
programming/erasing
When the CPU loses the bus during programming/erasing
RD VF PR ER FLER = 0
Normal operating mode
Verify-read possible
Program mode
Erase mode
occurrence
RD VF PR ER FLER = 1
Error protection mode
Error
P = 1 or
E = 1
Figure 17.23 Flash Memory State Transitions
P = 0 and
E = 0
Error occurrence
(software standby)
RD VF PR ER FLER = 0
RD: Memory read not possible
VF:
PR: Programming not possible
ER: Erasing not possible
RES = 0 or STBY = 0
read verify mode
Software
standby mode
Software standby
mode release
Verify-read not possible
Memory
Reset release and
hardware standby release
and software standby release
RES = 0 or
STBY = 0
RES = 0 or
FLMCR1, FLMCR2 (except FLER
bit), EBR1, EBR2 initialization state
RD VF PR ER FLER = 1
STBY = 0
Error protection mode
(software standby)
Reset or hardware standby
RD VF PR ER FLER = 0
RES = 0 or STBY = 0
(hardware protection)
or software standby
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
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