HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 435

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

12.2.6
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset, and in standby mode or module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
0
1
Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)
request and receive error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
0
1
Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF
Bit
Initial value
R/W
clearing it to 0, or clearing the TIE bit to 0.
flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Serial Control Register (SCR)
Description
Transmit data empty interrupt (TXI) requests disabled*
Transmit data empty interrupt (TXI) requests enabled
Description
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled*
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
:
:
:
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0
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