HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 541

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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15.2
15.2.1
DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion.
Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the
analog output pins.
DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode.
15.2.2
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset and in hardware standby mode.
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel
1.
Bit 7
DAOE1
0
1
528
Bit
Initial value
R/W
Bit
Initial value
R/W
Register Descriptions
D/A Data Registers 0 and 1 (DADR0, DADR1)
D/A Control Register (DACR)
Description
Analog output DA1 is disabled
Channel 1 D/A conversion is enabled; analog output DA1 is enabled
:
:
:
:
:
:
DAOE1
R/W
R/W
7
0
7
0
DAOE0
R/W
R/W
6
0
6
0
DAE
R/W
R/W
5
0
5
0
R/W
4
0
4
1
R/W
3
0
3
1
R/W
2
0
2
1
R/W
1
0
1
1
(Initial value)
R/W
0
0
0
1

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