HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 514

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and
transmit mode as described below.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
500
Retransfer operation when SCI is in receive mode
Figure 13.11 illustrates the retransfer operation when the SCI is in receive mode.
set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The
PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DTC data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared
to 0.
error signal transmission.
RDRF
PER
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 13.11 Retransfer Operation in SCI Receive Mode
nth transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransferred frame
(DE)
[4]
[3]
Ds D0 D1 D2 D3 D4
Transfer
frame n+1