HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 255

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.6.2
Table 8.9 shows the port A register configuration.
Table 8.9
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Notes: 1. Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are
reserved.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR
is used to select whether the address output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
238
Bit
Initial value
R/W
Modes 1, 2, 3, and 7*
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to
PA0DDR.
2. Lower 16 bits of the address.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
Register Configuration
Port A Registers
:
:
:
Undefined
—
—
7
Undefined
—
—
6
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
Undefined
—
—
5
Undefined
—
—
4
R/W
W
R/W
R
R/W
R/W
PA3DDR
W
3
0
Initial Value*
H'0
H'0
Undefined
H'0
H'0
PA2DDR
W
2
0
PA1DDR
1
W
1
0
Address*
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
PA0DDR
W
0
0
2