HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 310

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

9.2.3
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR
registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR
registers are initialized to H'00 by a reset, and in hardware standby mode.
Care is required since TIOR is affected by the TMDR setting. The initial output specified by
TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in
PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0)
Bits IOB3 to IOB0 specify the function of TGRB.
Bits IOD3 to IOD0 specify the function of TGRD.
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Channel 3: TIOR3H
Channel 4: TIOR4
Channel 5: TIOR5
Bit
Initial value
R/W
Channel 0: TIOR0L
Channel 3: TIOR3L
Bit
Initial value
R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
TIOR0H
register operates as a buffer register.
Timer I/O Control Register (TIOR)
I/O Control D3 to D0 (IOD3 to IOD0):
:
:
:
:
:
:
IOB3
IOD3
R/W
R/W
7
0
7
0
IOD2
IOB2
R/W
R/W
6
0
6
0
IOB1
IOD1
R/W
R/W
5
0
5
0
IOD0
IOB0
R/W
R/W
4
0
4
0
IOA3
IOC3
R/W
R/W
3
0
3
0
IOA2
IOC2
R/W
R/W
2
0
2
0
IOC1
IOA1
R/W
R/W
1
0
1
0
IOC0
IOA0
R/W
R/W
0
0
0
0
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