HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 630

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 6
STS2
0
1
Note: * Not used on the F-ZTAT version.
Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus
control signals (CS0 to CS3, AS, RD, HWR, LWR) is retained or set to the high-impedance state
in software standby mode.
Bit 3
OPE
0
1
Bits 2 and 1—Reserved: Read-only bits, always read as 0.
Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.
19.2.2
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
620
Bit
Initial value
R/W
Bit 5
STS1
0
1
0
1
System Clock Control Register (SCKCR)
Description
In software standby mode, address bus and bus control signals are high-impedance
In software standby mode, address bus and bus control signals retain output state
:
:
:
PSTOP
R/W
Bit 4
STS0
0
1
0
1
0
1
0
1
7
0
Description
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states*
R/W
—
6
0
—
—
5
0
—
—
4
0
—
—
3
0
SCK2
R/W
2
0
SCK1
R/W
1
0
(Initial value)
(Initial value)
SCK0
R/W
0
0