HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 423

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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11.4
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
11.5
11.5.1
If a timer counter clock pulse is generated during the T
takes priority and the timer counter is not incremented. Figure 11.8 shows this operation.
11.5.2
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
408
Interrupts
Usage Notes
Contention between Timer Counter (TCNT) Write and Increment
Changing Value of CKS2 to CKS0
ø
Address
Internal write signal
TCNT input clock
TCNT
Figure 11.8 Contention between TCNT Write and Increment
TCNT write cycle
T
1
N
2
T
state of a TCNT write cycle, the write
2
Counter write data
M

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