HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 335

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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9.2.8
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.
TSTR is initialized to H'00 by a reset, and in hardware standby mode.
Note: When setting the operating mode in TMDR or setting the count clock in TCR, first stop
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn
0
1
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
318
Bit
Initial value
R/W
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
the TCNT counter.
Timer Start Register (TSTR)
Description
TCNTn count operation is stopped
TCNTn performs count operation
:
:
:
7
0
6
0
CST5
R/W
5
0
CST4
R/W
4
0
CST3
R/W
3
0
CST2
R/W
2
0
CST1
R/W
1
0
(Initial value)
CST0
n = 5 to 0
R/W
0
0

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