HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 309

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 5
BFB
0
1
Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot
be modified.
Bit 4
BFA
0
1
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3
MD3*
0
1
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
292
1
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
Bit 2
MD2*
0
1
*
be written to MD2.
Description
TGRB operates normally
TGRB and TGRD used together for buffer operation
Description
TGRA operates normally
TGRA and TGRC used together for buffer operation
2
Bit 1
MD1
0
1
0
1
*
Bit 0
MD0
0
1
0
1
0
1
0
1
*
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
—
Description
Normal operation
(Initial value)
(Initial value)
(Initial value)
*: Don’t care