HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 131

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Figure 5.3 shows the timing of setting IRQnF.
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
5.3.2
There are 43 sources for internal interrupts from on-chip supporting modules.
5.3.3
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. The situation when two or more
modules are set to the same priority, and priorities within a module, are fixed as shown in
table 5.4.
112
input pin
For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
The interrupt priority level can be set by means of IPR.
The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the
DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not
affected.
IRQnF
IRQn
ø
Internal Interrupts
Interrupt Exception Handling Vector Table
Figure 5.3 Timing of Setting IRQnF