HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 202

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 7.2 outlines the functions of the DTC.
Table 7.2
Transfer Mode
184
Normal mode
Repeat mode
Block transfer mode
One transfer request transfers one
Memory addresses are incremented
Up to 65,536 transfers possible
One transfer request transfers one
Memory addresses are incremented
After the specified number of
One transfer request transfers a block
Block size is from 1 to 256 bytes or
Up to 65,536 transfers possible
A block area can be designated at
byte or one word
or decremented by 1 or 2
byte or one word
or decremented by 1 or 2
transfers (1 to 256), the initial state
resumes and operation continues
of the specified size
words
either the source or destination
DTC Functions
Activation Source
IRQ
TPU TGI
8-bit timer CMI
SCI TXI or RXI
A/D converter ADI
Software
Transfer
Source
24 bits
Address Registers
Transfer
Destination
24 bits