HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 150

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.1
The H8S/2345 Series has a built-in bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU and data transfer controller (DTC).
6.1.1
The features of the bus controller are listed below.
Note: * ZTAT, mask ROM, and ROMless versions only.
Manages external address space in area units
Basic bus interface
Burst ROM interface
Idle cycle insertion
Bus arbitration function
Other features
In advanced mode, manages the external space as 8 areas of 2-Mbytes
In normal mode*, manages the external space as a single area
Bus specifications can be set independently for each area
Chip select (CS0 to CS3) can be output for areas 0 to 3
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted in case of an external write cycle immediately after an
Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC
External bus release function
external read cycle
Overview
Features
Section 6 Bus Controller
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