HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 493

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
Smart Card interface mode.
Bit 4
ERS
0
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial
Status Register (SSR).
However, the setting conditions for the TEND bit, are as shown below.
Bit 2
TEND
0
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
state.
Description
Indicates that data was received normally and no error signal was sent
[Clearing condition]
Indicates that an error signal was sent from the receiving side showing that a parity
error was detected
[Setting condition]
When the low level of the error signal is sampled
Description
Indicates data transmission in progress
[Clearing conditions]
Indicates that data transmission is finished
[Setting conditions]
Upon reset, and in standby mode or module stop mode
When 0 is written to ERS after reading ERS = 1
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
Upon reset, and in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is also 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial
character is transmitted when GM = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial
character is transmitted when GM = 1.
(Initial value)
(Initial value)
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