HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 198

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

7.2.6
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7
The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
180
Bit
Initial value
R/W
Bit
Initial value
R/W
DTC Transfer Count Register B (CRB)
DTC Enable Registers (DTCER)
:
:
:
:
:
:
Unde-
fined
15
—
DTCE7
R/W
Unde-
fined
14
—
7
0
Unde-
fined
13
—
DTCE6
R/W
Unde-
fined
6
0
12
—
Unde-
fined
11
—
DTCE5
R/W
Unde-
5
0
fined
10
—
Unde-
fined
—
9
DTCE4
R/W
4
0
Unde-
fined
—
8
Unde-
fined
DTCE3
—
7
R/W
3
0
Unde-
fined
—
6
Unde-
fined
DTCE2
—
5
R/W
2
0
Unde-
fined
—
4
Unde-
DTCE1
fined
—
R/W
3
1
0
Unde-
fined
—
2
DTCE0
Unde-
fined
R/W
—
1
0
0
Unde-
fined
—
0