HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 639

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

19.8
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,
and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.
Table 19.5 shows the state of the ø pin in each processing state.
Table 19.5 ø Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
Oscillator
RES
STBY
ø Clock Output Disabling Function
Figure 19.3 Hardware Standby Mode Timing (Example)
0
—
High impedance
High impedance
High impedance
High impedance
1
0
Fixed high
ø output
ø output
Oscillation
stabilization
time
1
Fixed high
Fixed high
exception
handling
Reset
629