HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 621

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

18.2
18.2.1
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus
master.
Bit 2
SCK2
0
1
610
Bit
Initial value
R/W
Register Descriptions
System Clock Control Register (SCKCR)
Bit 1
SCK1
0
1
0
1
Normal Operation
ø output (initial value)
Fixed high
:
:
:
PSTOP
R/W
Bit 0
SCK0
0
1
0
1
0
1
—
7
0
R/W
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
—
6
0
Sleep Mode
ø output
Fixed high
—
—
5
0
Description
—
—
4
0
Software
Standby Mode
Fixed high
Fixed high
—
—
3
0
SCK2
R/W
2
0
SCK1
Hardware
Standby Mode
High impedance
High impedance
R/W
1
0
(Initial value)
SCK0
R/W
0
0