HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 215

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 7.9
Object to be Accessed
Bus width
Access states
Execution Vector read
status
The number of execution states is calculated from the formula below. Note that
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Number of execution states = I · S
Register
information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
Number of States Required for Each Execution Status
S
S
S
S
S
S
I
J
K
K
L
L
M
On-
Chip
RAM
32
1
—
1
1
1
1
1
1
I
+
On-
Chip
ROM
16
1
1
—
1
1
1
1
(J · S
On-Chip I/O
Registers
8
2
—
—
2
4
2
4
J
+ K · S
16
2
—
—
2
2
2
2
K
+ L · S
External Devices
8
2
4
—
2
4
2
4
L
) + M · S
3
6+2m 2
—
3+m
6+2m 2
3+m
6+2m 2
M
means the sum
16
2
—
2
2
3
3+m
—
3+m
3+m
3+m
3+m
197