HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 257

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Port A MOS Pull-Up Control Register (PAPCR)
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
Bits 3 to 0 are valid in modes 1, 2, 3, 6, and 7, and all the bits are invalid in modes 4 and 5. When
a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on
the MOS input pull-up for the corresponding pin.
PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port A Open Drain Control Register (PAODR)
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
All bits are valid in modes 1, 2, 3, and 7.*
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
240
Bit
Initial value
R/W
Bit
Initial value
R/W
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
:
:
:
3
to PA
Undefined
Undefined
—
—
—
—
7
7
0
).
Undefined
Undefined
—
—
—
—
6
6
Undefined
Undefined
—
—
—
—
5
5
Undefined
Undefined
—
—
—
—
4
4
PA3ODR
PA3PCR
R/W
R/W
3
0
3
0
PA2ODR
PA2PCR
R/W
R/W
2
0
2
0
PA1ODR
PA1PCR
R/W
R/W
1
0
1
0
PA0ODR
PA0PCR
R/W
R/W
0
0
0
0