HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 212

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

7.3.8
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.9 shows the memory map for chain transfer.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
194
DTC vector
address
Chain Transfer
Register information
start address
Figure 7.9 Chain Transfer Memory Map
Register information
Register information
CHNE = 1
CHNE = 0
Destination
Destination
Source
Source