HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 284

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Bit
Initial value
R/W
Modes 1, 2, 4, 5, and 6*
Pin PF
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF
means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the
corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7*
Setting a PFDDR bit to 1 makes the corresponding port F pin PF
the case of pin PF
Modes 2, 3, 6, and 7 are not available on the ROMless version.
7
2
functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
to PF
:
:
:
0
PF7DR
are designated as bus control input/output pins (WAIT, BACK, BREQ) by
R/W
7
7
0
, the ø output pin. Clearing the bit to 0 makes the pin an input port.
PF6DR
R/W
6
0
PF5DR
R/W
5
0
PF4DR
R/W
4
0
PF3DR
R/W
3
0
6
PF2DR
to PF
R/W
2
0
6
to PF
0
an output port, or in
PF1DR
R/W
3
, which are
1
0
PF0DR
7
to PF
R/W
0
0
0
267
).