HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 576

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 0
PSU
0
1
17.7.3
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and
2 in EBR1 and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized
to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is
input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1
is cleared to 0. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Blocks are erased separately (in one-block units), so set only one bit in
EBR1 or EBR2 (more than one bit cannot be set to 1). To erase all blocks, erase one block at a
time, once after another in sequence. Then on-chip flash memory is disabled (modes 4 and 5), a
read with return H'00, and writes are disabled.
The flash memory block configuration is shown in table 17.12.
564
Bit
EBR1
Initial value
Read/Write
Bit
EBR2
Initial value
Read/Write
Erase Block Registers 1 and 2 (EBR1, EBR2)
Description
Program setup cleared
Program setup
[Setting condition]
When FWE = 1, and SWE = 1
EB7
R/W
—
—
7
0
7
0
EB6
R/W
—
—
6
0
6
0
EB5
R/W
—
—
5
0
5
0
EB4
R/W
—
—
4
0
4
0
EB3
R/W
—
—
3
0
3
0
EB2
R/W
—
—
2
0
2
0
EB9
R/W
EB1
R/W
1
0
1
0
(Initial value)
EB8
R/W
EB0
R/W
0
0
0
0