HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 471

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

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Figure 12.12 Sample Multiprocessor Serial Reception Flowchart
Read ORER and FER flags in SSR
Read ORER and FER flags in SSR
Read receive data in RDR
Read receive data in RDR
Read RDRF flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read MPIE bit in SCR
All data received?
This station's ID?
FER ORER= 1
FER ORER= 1
Start reception
Initialization
RDRF= 1
RDRF= 1
<End>
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Yes
Yes
Yes
No
No
Yes
No
Yes
Error processing
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SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
ID reception cycle:
Set the MPIE bit in SCR to 1.
SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Receive error processing and
break detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
processing, ensure that the
ORER and FER flags are all
cleared to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
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