HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 93

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.2.2
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Bits 2 and 1—Reserved: Only 0 should be written to these bits.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Bit
Initial value
R/W
System Control Register (SYSCR)
Bit 4
INTM0
0
1
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
R/W
—
7
0
Interrupt
Control Mode
0
—
2
—
R/W
—
6
0
INTM1
R/W
5
0
Description
Control of interrupts by I bit
Setting prohibited
Control of interrupts by I2 to I0 bits and IPR
Setting prohibited
INTM0
R/W
4
0
NMIEG
R/W
3
0
R/W
—
2
0
R/W
—
1
0
(Initial value)
(Initial value)
(Initial value)
RAME
R/W
0
1
73