HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 161

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 5
EAE
0
1
Note: * Reserved areas should not be accessed.
Bits 4 to 2—Reserved: Only 1 should be written to these bits.
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
0
1
6.3
6.3.1
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to
7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it
controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the
memory map.
Chip select signals (CS0 to CS3) can be output for areas 0 to 3.
Note: * ZTAT, mask ROM, and ROMless versions only.
142
Overview of Bus Control
Area Partitioning
Description
Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2345)
Addresses H'010000 to H'017FFF are in on-chip ROM and addresses H'018000 to
H'01FFFF are a reserved area (in the H8S/2344)
Addresses H'010000 to H'01FFFF are a reserved area (in the H8S/2343 and
H8S/2341)
Addresses H'010000 to H'01FFFF are external addresses (external expansion mode)
or a reserved area* (single-chip mode)
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
Wait input by WAIT pin enabled
(Initial value)
(Initial value)