HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 256

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA
PA
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port A Register (PORTA)
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset,
and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PA
0
Mode 6*
Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing
the bit to 0 makes the pin an input port.
).
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
:
:
:
Undefined
Undefined
—
—
—
—
7
7
Undefined
Undefined
—
—
—
—
6
6
3
to PA
Undefined
Undefined
3
—
—
—
—
5
to PA
5
0
) must always be performed on PADR.
0
Undefined
Undefined
.
—
—
—
—
4
4
PA3DR
PA3
R/W
—*
R
3
3
0
PA2DR
PA2
R/W
—*
R
2
2
0
PA1DR
PA1
R/W
—*
R
1
1
0
PA0DR
3
PA0
R/W
—*
to
R
0
0
0
239