MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 114
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MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Device Overview MC9S12G-Family
1.12.3
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.12.3.1
On each reset, the Flash module holds CPU activity while loading Flash module registers from the Flash
memory. If double faults are detected in the reset phase, Flash module protection and security may be
active on leaving reset. This is explained in more detail in the Flash module
1.12.3.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.12.3.3
Refer to the PIM section for reset configurations of all peripheral module ports.
1.12.3.4
The RAM arrays are not initialized out of reset.
1.13
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash register FOPT. See
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.
114
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
COP Configuration
Effects of Reset
Flash Configuration Reset Sequence Phase
Reset While Flash Command Active
I/O Pins
RAM
FOPT Register
NV[2:0] in
Table 1-29. Initial COP Rate Configuration
MC9S12G Family Reference Manual,
000
001
010
011
100
101
110
111
Table 1-29
and
CPMUCOP Register
Table 1-30
CR[2:0] in
111
110
101
100
011
010
001
000
Rev.1.01
for coding. The FOPT register is
Section 26.1,
Freescale Semiconductor
“Introduction”.
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