MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 400
MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Analog-to-Digital Converter (ADC10B12CV2)
12.2
This section lists all inputs to the ADC10B12C block.
12.2.1
12.2.1.1
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
12.2.1.2
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connectivity of these inputs!
12.2.1.3
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
12.2.1.4
These pins are the power supplies for the analog circuitry of the ADC10B12C block.
12.3
This section provides a detailed description of all registers accessible in the ADC10B12C.
12.3.1
Figure 12-2
400
Address
0x0000
0x0001
0x0002
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Signal Description
Memory Map and Register Definition
ATDCTL0
ATDCTL1
ATDCTL2
Detailed Signal Descriptions
Module Memory Map
Name
gives an overview on all ADC10B12C registers.
ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
ETRIG3, ETRIG2, ETRIG1, ETRIG0
VRH, VRL
VDDA, VSSA
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
W
W
W
R
R
R
Figure 12-2. ADC10B12C Register Summary (Sheet 1 of 3)
ETRIGSEL
Reserved
Bit 7
0
MC9S12G Family Reference Manual,
= Unimplemented or Reserved
SRES1
AFFC
6
0
Reserved ETRIGLE
SRES0
5
0
NOTE
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
4
0
ETRIGP
WRAP3
Rev.1.01
3
ETRIGE
WRAP2
2
Freescale Semiconductor
WRAP1
ASCIE
1
ACMPIE
WRAP0
Bit 0
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