MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 574

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Communication Interface (S12SCIV5)
18.3.2.6
Read: Anytime
Write: Anytime
574
Module Base + 0x0003
Reset
Field
TCIE
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
ILIE
RIE
TIE
RE
TE
7
6
5
4
3
2
W
R
BERRM1
Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
TIE
1
SCI Control Register 2 (SCICR2)
0
7
BERRM0
TCIE
1
0
6
Figure 18-9. SCI Control Register 2 (SCICR2)
Reserved
MC9S12G Family Reference Manual,
Table 18-10. SCICR2 Field Descriptions
Table 18-9. Bit Error Mode Coding
RIE
5
0
ILIE
0
4
Description
Function
TE
0
3
Rev.1.01
RE
2
0
Freescale Semiconductor
RWU
0
1
SBK
0
0