MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 883
MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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25.3.2.9.1
The general guideline is that P-Flash protection can only be added and not removed.
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
25.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
1
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
Freescale Semiconductor
Loaded from IFR Flash configuration field, during reset sequence.
Offset Module Base + 0x0009
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
DPOPEN
F
7
1
P-Flash Protection Restrictions
1
Protection
Allowed transitions marked with X, see
Scenario
From
0
1
2
3
4
5
6
7
F
6
Figure 25-15. EEPROM Protection Register (EEPROT)
Table 25-21. P-Flash Protection Scenario Transitions
1
0
X
X
MC9S12G Family Reference Manual, Rev.1.01
F
5
1
X
X
X
X
1
X
X
X
X
2
To Protection Scenario
F
4
1
Figure 25-14
X
X
X
X
X
X
X
X
3
DPS[6:0]
X
X
X
X
F
4
for a definition of the scenarios.
3
1
1
X
X
5
96 KByte Flash Module (S12FTMRG96K1V1)
F
2
1
X
X
6
Table 25-21
7
X
F
1
1
specifies
F
0
1
883
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