MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 642

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Timer Module (TIM16B8CV3)
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
20.3.2.8
Read: Anytime
Write: Anytime
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
642
TOV[7:0]
Reset
Reset
Field
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
OMx
OLx
7:0
7:0
7:0
unavailable bits return a zero.
unavailable bits return a zero
W
W
R
R
OM7
OM3
Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override
events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
0
0
7
7
an output line to be driven by an OCx the OCPDx must be cleared.
an output line to be driven by an OCx the OCPDx must be cleared.
OL7
OL3
0
0
6
6
Figure 20-14. Timer Control Register 1 (TCTL1)
Figure 20-15. Timer Control Register 2 (TCTL2)
Table 20-8. TCTL1/TCTL2 Field Descriptions
MC9S12G Family Reference Manual,
Table 20-7. TTOV Field Descriptions
OM6
OM2
5
0
5
0
OL6
OL2
0
0
4
4
Description
Description
OM5
OM1
0
0
3
3
Rev.1.01
OL5
OL1
2
0
2
0
Freescale Semiconductor
OM4
OM0
0
0
1
1
OL4
OL0
0
0
0
0