MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 623

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
MOSI pin
MISO pin
Figure 19-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0)
MSB first (LSBFE = 0):
t
t
t
LSB first (LSBFE = 1):
L
T
I
= Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
= Minimum leading time before the first SCK edge, not required for back-to-back transfers
= Minimum trailing time after the last SCK edge
t
L
1
MSB
LSB
2
3
MC9S12G Family Reference Manual, Rev.1.01
Begin
Bit 6
Bit 1
4
5
Bit 5
Bit 2
6
7
Bit 4
Bit 3
8
Transfer
9
Bit 3
Bit 4
10
11
Bit 2
Bit 5
12
13 14
Bit 1
Bit 6
End
Serial Peripheral Interface (S12SPIV5)
15
MSB
LSB
16
t
T
Minimum 1/2 SCK
Begin of Idle State
t
I
for t
T
t
L
, t
l
, t
L
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