MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 285

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3.2.2
Read: Anytime
Write: Never
Freescale Semiconductor
Address: 0x0021
SSF[2:0]
COMRV
Reset
Field
Field
POR
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
TBF
1–0
2–0
7
W
R
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGCNT[7]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
Debug Status Register (DBGSR)
—
0
7
COMRV
00
01
10
11
= Unimplemented or Reserved
0
0
0
6
Figure 8-4. Debug Status Register (DBGSR)
Visible Comparator
MC9S12G Family Reference Manual, Rev.1.01
Table 8-4. DBGSR Field Descriptions
Table 8-2. DBGC1 Field Descriptions
Comparator A
Comparator B
Comparator C
5
0
0
0
Table 8-3. COMRV Encoding
None
0
0
0
4
Description
Description
Visible Register at 0x0027
0
0
0
3
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SSF2
8-3.
Table 8-5
2
0
0
S12S Debug Module (S12SDBG)
.
SSF1
0
0
1
SSF0
0
0
0
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