MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 589

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

18.4.6
18.4.6.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
18.4.6.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
Freescale Semiconductor
From TXD Pin
or Transmitter
SCRXD
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
LOOPS
RSRC
Receiver
Receiver Character Length
Character Reception
RXPOL
Control
SBR12:SBR0
Loop
Clock
Bus
Baud Divider
Figure 18-20. SCI Receiver Block Diagram
WAKE
MC9S12G Family Reference Manual, Rev.1.01
RAF
RE
ILT
PE
PT
M
Recovery
Detect Logic
Data
Detect Logic
Active Edge
Break
BRKDFE
Checking
Wakeup
Parity
Logic
Internal Bus
H
RXEDGIF
RXEDGIE
BRKDIE
BRKDIF
8
RDRF
11-Bit Receive Shift Register
7
OR
Serial Communication Interface (S12SCIV5)
SCI Data Register
6
5
4
FE
NF
PE
3
R8
IDLE
ILIE
RIE
2
Break IRQ
RX Active Edge IRQ
1
0
L
RWU
RDRF/OR
Idle IRQ
IRQ
589