MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 365

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.4.3
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure
10.4.4
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in
Freescale Semiconductor
LOCK
System
Reset
LOCK
SYNDIV
POSTDIV $03 (default target f
CPU
PLLCLK
PLLCLK
CPU
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
10-31. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
execution
Figure
f
VCORST
Stop Mode using PLLCLK as Bus Clock
Full Stop Mode using Oscillator Clock as Bus Clock
$18 (default target f
reset state
768 cycles
10-32.
) (
STOP instruction
Figure 10-31. Stop Mode using PLLCLK as Bus Clock
wakeup
Figure 10-30. Startup of clock system after Reset
VCO
PLL
MC9S12G Family Reference Manual, Rev.1.01
=f
vector fetch, program execution
=50MHz)
VCO
/4 = 12.5MHz)
t
STP_REC
f
PLL
increasing
t
lock
interrupt
S12 Clock, Reset and Power Management Unit (S12CPMU)
t
lock
continue execution
f
PLL
=16MHz
example change
of POSTDIV
$01
f
PLL
=32 MHz
365